1. Field of the Invention
The present invention relates to a memory cell array and to a method of making the same, and in particular to such a memory cell array the memory cells of which are addressable individually.
2. Description of Prior Art
Non-volatile memories (NVM; NVM=non-volatile memories) are broadly used nowadays, with floating-gate memory cells being utilized in particular. A distinction is made between two types of memory modules, data memories on the one hand and program memories on the other hand.
In case of data memories, it is necessary that small memory units, for example individual bits, 1 byte consisting of 8 bits, or a word consisting of 128 bits, must be erasable and programmable in freely selectable manner, which may lead to numerous reprogramming cycles.
In contrast thereto, in case of program memories, which are realized mainly in the form of flash memories, only large units, for example a sector with 512 bits, can be erased as a whole before bitwise writing or programming takes place. For example, if only 1 byte is to be written anew, the entire sector has to be erased and re-written. This means unnecessary burdening of the cells that actually were not to be addressed. The lifetime thereof is reduced considerably thereby. The functionality of a program memory is thus restricted. In contrast thereto, higher storage density can be realized with a flash memory since smaller cell areas are necessary.
In the scope of the present application, the erasure of a memory cell is to be understood as being the respective process in which charges are introduced into the memory medium, which is the floating gate in case of the floating-gate memory cells mentioned, of a memory cell. Writing or programming is to be understood as the process in which corresponding charges are removed, i.e. extracted, from the memory medium.
For realizing data memories in which small memory units have to be erasable and programmable in freely selective manner, it is known to arrange such memory units in a word line and separate them by so-called byte switches. However, such byte switches result in the memory module being increased considerably.
As an alternative to byte switches, it is known from the prior art to employ split voltages, i.e. to supply for selective programming and erasing, respectively, part of the voltage via the word line and another part via the bit line of a memory cell.
An example of an architecture using such split voltages will be elucidated hereinafter in more detail with reference to FIGS. 6a and 6b which schematically illustrate a section of a memory cell array comprising four memory cells 1, 2, 3 and 4. In FIG. 6a, the voltages applied are shown for erasure of the encircled memory cell 1, whereas FIG. 6b shows the voltages applied for programming of the encircled memory cell 1.
The memory cells 1 to 4 are, for example, conventional n-channel EEPROM memory cells of the flotox type (flotox=floating gate tunnel oxide). Such memory cells have tunnel injection areas that are not shown. With such n-channel EEPROM cells, in accordance with the terminology used herein, programming is equivalent to the extraction of electrons from the floating gate, whereas erasure is equivalent to the application of electrons to the floating gate. Word lines and bit lines are provided for application of the necessary voltages.
As illustrated in FIGS. 6a and 6b, the control gates 5 of memory cells 1 and 2 arranged in a row are connected to a word line WL, whereas the control grates 5 of the memory cells 3 and 4 arranged in the row therebelow are connected to a word line WL′. Furthermore, the source regions of the memory cells 1 and 3 arranged in the left-hand column are connected to a first bit line BL1, while the drain regions thereof are connected to a second bit line BL2. In like manner, the source regions of the memory cells 2 and 4 arranged in the right-hand column are connected to a first bit line BL1′, while the drain regions thereof are connected to a second bit line BL2′.
For selectively programming or erasing a memory cell, suitable voltages are supplied via an associated word line and the two associated bit lines, so that only for the memory cell located at the respective point of intersection of the word lines and the two bit line, there is applied a sufficiently high potential difference both at the control gate and at the drain region for effecting erasure or programming, respectively, of the respective memory cell by means of a Fowler-Nordheim tunneling effect. Neither the drain potential alone nor the control gate potential alone are sufficient for effecting such tunneling, so that the desired effect occurs only at the memory cell located at the point of intersection.
FIG. 6a illustrates two cases a) and b) of voltages applied to the word lines and bit lines for erasure of the encircled memory cell 1.
In the first case a), a voltage of +10V is applied to the word line WL associated with the cell 1 to be erased, and a voltage of −6V is applied to the associated bit line BL1, whereas the associated bit line BL2 is floating. A voltage of 0V is applied to word line WL′ and bit line BL1′, and bit line BL2′ is floating.
In the second case b), a voltage of +16V is applied to the word line WL associated with memory cell 1 to be erased, and a voltage of 0V is applied to the associated bit line BL1, whereas the associated bit line BL2 is floating. A voltage of 0V is applied to word line WL′, a voltage of +6V is applied to bit line BL1′, and bit line BL2′ is floating.
As shown in FIG. 6b for programming of the selected cell 1, a voltage of −10V is applied to the associated word line WL, whereas a voltage of +6V is applied to the associated bit line BL1 and the associated bit line BL2 is floating. The word line WL′ and the bit lines BL1′ and BL2′ have a potential of 0V each.
In addition to the split voltages to be applied to word lines and bit lines, as described hereinbefore with reference to FIGS. 6a and 6b, it is necessary in addition that the potentials suitable for erasure are applied to the tunnel windows of the memory cells. In case of erasure as in case b), positive potentials have to be applied as so-called inhibit voltage to the tunnel window of cells not to be erased, whereas in case a) negative potentials have to be applied to the tunnel window of the cell addressed for erasure thereof. Negative potentials in general cannot be applied to a bit line in selective manner since the source/drain regions are polarized in forward direction.
For supplying a positive potential to the tunnel window, a highly doped n+ injection area is necessary below the tunnel window, which causes an increase in area of the cell. This increase in area may be reduced by utilizing the drain overlap and the source overlap, respectively, as injection area, which however results in a reliability problem in erasure due to the high current density. If the injection area mentioned is dispensed with completely, a positive potential can be applied to the tunnel oxide of the cell via the well only. Positive potentials require a p-well in a deep n-well, which results in a so-called “triple well”, thereby increasing process complexity. Such a technology using an isolated p-well structure for each cell column is described by Chi-Nan Brian Li et al. “A Novel Uniform-Channel-Program-Erase (UCPE) Flash EEPROM Using An Isolated P-Well Structure, Conference Proceedings of IEDM 2000, San Francisco, 10th to 13th Dec. 2000.
Individual isolation of wells under a cell would require an immense amount of space. Thus, only the selection of large memory blocks is possible.
Without the use of an injection area, suitable split voltage conditions in erasing a cell may also be achieved by exploiting the fact that, in case b) of FIG. 6a, a channel is created at the memory cell 2 via which the positive potential can be supplied to the cell. However, this is no longer possible in writing since, with negative voltages, there is no channel created at the control gate. Positive or negative voltages must then be supplied via the well. Thus, in this case too, only large memory blocks can be globally erased.
If there are no split voltages utilized, a high voltage can be supplied via respective bit lines to effect Fowler-Nordheim tunneling; however, this high voltage then has to be blocked away from the cells not addressed by means of select gates.
A memory cell array based on an SOI wafer (SOI=silicon-on-insulator) is described in U.S. Pat. No. 5,796,142. In case of the memory cell array described there, the source/drain regions of the memory transistors are formed in the silicon layer of an SOI wafer down to the insulating layer thereof. Thus, strip-shaped substrate regions are formed between the respective source/drain regions which are separated from each other by the source/drain regions, so that the substrate regions of a row of memory cells are isolated from the substrate regions of an adjacent row of memory cells. Thus, it is possible to apply suitable voltages to the word line connected to the control gate of a particular cell and to the strip-shaped substrate region or the substrate line of the respective memory cell, in order to effect both an erase and a programming operation between the floating gate and the substrate on the basis of the Fowler-Nordheim tunneling effect.
From JP 09 116120 A (and the associated Patent Abstracts of Japan, Vol. 1997, Nov. 9, Sep. 30, 1997), a memory cell array is known in which the source regions, the drain regions, and the substrate regions are separated from each other along word lines of adjacent memory cells by oxide regions. In the direction perpendicular to the word lines, the drain regions are continuously formed as data line, the source regions are continuously formed as source line, and the substrate regions are continuously formed as substrate line. For programming or erasing of respective memory cells, appropriate voltages are applied to the word lines, data lines, source lines, and substrate lines.
From JP 09 213910 A (and the associated Patent Abstracts of Japan, Vol. 1997, Nov. 12, Dec. 25, 1997), a memory cell array is also known in which the substrate regions are isolated from each other from memory transistors adjacent along word lines by oxide regions. Substrate regions perpendicularly adjacent to the word lines are connected to each other. For programming or erasing of memory cells, respective voltages are applied to word lines, substrate regions of the transistors, and bit lines.
Form U.S. Pat. No. 5,760,437, a memory cell array is known which is realized on a semiconductor substrate, the drain/source regions of the memory cells being formed in a surface of the semiconductor substrate. The channel substrate regions associated with adjacent memory cells are not isolated from each other.